This invention relates generally to binary counters and more particularly, it relates to a high speed, low power loadable, single edge-triggered, wraparound, binary counter.
As is well known, counters are useful in a variety of logic or control systems such as special or general-purpose digital computers, electronic calculators, digital electronic switching systems or digital electronic control systems. With the advent of large scale integration (LSI) technology, such counters may be formed together with other analog and digital circuitry on a single silicon chip of an integrated circuit device. As a result, there has arisen the need to construct a counter which is capable of high speed operation and has low power dissipation. It would also be desirable to provide a fully bit-sliced binary counter in which the number of counter cells may be increased to any desired bit-count in a simple manner so as to facilitate design, layout and manufacturing, thereby reducing cost and enhancing reliability.